? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 1 of 8 silicon carbide junction transistor/schottky diode co-pack features package ? 175c maximum operating temperature ? gate oxide free sic switch ? exceptional safe operating area ? integrated sic schottky rectifier ? excellent gain linearity ? temperature independent switching performance ? low output capacitance ? positive temperature co-efficient of r ds,on ? suitable for connecting an anti-parallel diode ? to-263 ? advantages applications ? compatible with si mosfet/igbt gate drive ics ? > 20 s short-circuit withstand capability ? lowest-in-class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? reduced cooling requirements ? reduced system size ? ? hybrid electric vehicles (hev) ? solar inverters ? switched-mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives absolute maximum ratings parameter symbol conditions values unit sic junction transistor drain ? source voltage v ds v gs = 0 v 1200 v continuous drain current i d 95 c < t c < 135 c 20 a gate peak current i gm 10 a turn-off safe operating area rbsoa t vj = 175 o c, i g = 1 a, clamped inductive load i d,max = 20 @ v ds v dsmax a short circuit safe operating area scsoa t vj = 175 o c, i g = 1 a, v ds = 800 v, non repetitive 20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v power dissipation p tot t c = 95 c 131 w storage temperature t stg -55 to 175 c free-wheeling silicon carbide diode dc-forward current i f t c 150 oc 20 a non repetitive peak forward current i fm t c = 25 oc, t p = 10 s 280 a surge non repetitive forward current i f,sm t p = 10 ms, half sine, t c = 25 oc 65 a thermal characteristics thermal resistance, junction - case r thjc sic junction transistor 0.61 c/w thermal resistance, junction - case r thjc sic diode 0.82 c/w g d s v ds = 1200 v r ds(on) = 60 m ? i d (tc = 25c) = 45 a h fe ? (tc ? = ? 25c) 60
? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 2 of 8 electrical characteristics parameter symbol conditions values unit min. typ. max. sjt on-state characteristics drain ? source on resistance r ds(on) i d = 20 a, i g = 1000 ma, t j = 25 c 60 m ? i d = 20 a, i g = 1000 ma, t j = 125 c 90 i d = 20 a, i g = 1000 ma, t j = 175 c 136 gate forward voltage v gs(fwd) i g = 1000 ma, t j = 25 c 3.1 v i g = 1000 ma, t j = 175 c 2.9 dc current gain h fe v ds = 5 v, i d = 20 a, t j = 25 c v ds = 5 v, i d = 20 a, t j = 175 c 60 37 sjt off-state characteristics drain leakage current i dss v r = 1200 v, v gs = 0 v, t j = 25 c v r = 1200 v, v gs = 0 v, t j = 125 c 0.1 0.2 1.0 1.0 1.0 ma v r = 1200 v, v gs = 0 v, t j = 175 c 0.5 gate leakage current i sg v sg = 20 v, t j = 25 c 20 na sjt capacitance characteristics input capacitance c iss v gs = 0 v, v d = 1 v, f = 1 mhz 482 pf output capacitance c oss v d = 100 v,00 f = 1 mhz 220 pf reverse transfer capacitance c rss v d = 100 v, f = 1 mhz 106 pf output capacitance stored energy e oss v gs = 0 v, v d = 100 v, f = 1 mhz 1.1 j sjt switching characteristics 1 gate resistance, internal r g ( int ) f = 1 mhz, v ac = 25 mv, t j = 175 oc 2.6 ? turn on delay time t d ( on ) v dd = 800 v, i d = 20 a, r g = 1.53 ? , c g = 9.0 nf fwd = ga20sicp12, t j = 25 oc refer to figure 15 for gate current waveform 15 ns rise time t r 20 ? ns turn off delay time t d ( off ) 30 ? ns fall time t f 50 ? ns turn-on energy per pulse e on 475 ? j turn-off energy per pulse e off 300 ? j total switching energy e ts 780 ? j turn on delay time t d ( on ) v dd = 800 v, i d = 20 a, r g = 1.53 ? , c g = 9.0 nf fwd = ga20sicp12, t j = 175 oc refer to figure 15 for gate current waveform 15 ? ns rise time t r 20 ? ns turn off delay time t d ( off ) 35 ? ns fall time t f 45 ? ns turn-on energy per pulse e on 515 ? j turn-off energy per pulse e off 290 ? j total switching energy e ts 805 ? j free-wheeling silicon carbide schottky diode (fwd) switching characteristics 1 forward voltage v f i f = 20 a, v ge = 0 v, t j = 25 oc (175 oc ) 1.9(3.3) v diode knee voltage v d ( knee ) t j = 25 oc, i f = 1 ma 0.8 v peak reverse recovery current i rrm i f = 20 a, v ge = 0 v, v r = 800 v, -di f /dt = 1060 a/s, t j = 25 oc 9.8 a reverse recovery time t rr 30 ns rise time t r v f = 800 v, i f = 20 a, r g = 1.53 ? , c g = 9.0 nf, t j = 25 oc 60 ns fall time t f 20 ns turn-on energy loss per pulse e on 70 j turn-off energy loss per pulse e off 50 j reverse recovery charge q rr 165 nc rise time t r v f = 800 v, i f = 20 a, r g = 1.53 ? , c g = 9.0 nf, t j = 175 oc 50 ns fall time t f 20 ns turn-on energy loss per pulse e on 75 j turn-off energy loss per pulse e off 50 j reverse recovery charge q rr 180 nc 1 ? times measured of co-pack currents i d and i f . ?
? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 3 of 8 figures figure 1: typical output characteristics at 25 c figure 2: typical output characteristics at 125 c figure 3: typical output characteristics at 175 c figure 4: typical gate source i-v characteristics vs. temperature figure 5: normalized on-resistance and current gain vs. temperature figure 6: typical blocking characteristics
? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 4 of 8 figure 7: capacitance characteristics figure 8: output capacitance stored energy figure 9: typical hard-switched turn on waveforms figure 10: typical hard-switched turn off waveforms figure 11: typical turn on energy losses and switching times vs. temperature figure 12: typical turn off energy losses and switching times vs. temperature ??
? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 5 of 8 ? figure 13: typical turn on energy losses vs. drain current figure 14: typical turn off energy losses vs. drain current figure 15: typical gate current waveform figure 16: typical hard switched device power loss vs. switching frequency 2 figure 17: power derating curve figure 18: forward bias safe operating area at t c = 95 o c 2 ? representative values based on device switching energy loss. actual losses will depend on gate drive conditions, device load , and circuit topology.
? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 6 of 8 figure 19: turn-off safe operating area figure 20: transient thermal impedance (sic junction transistor) figure 21: typical sic fwd forward characteristics fig. 22: transient thermal impedance characteristics (fwd)
? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 7 of 8 gate drive theory of operation for the GA20SICP12-263 the sjt transistor is a current controlled transistor which requires a positive gate curr ent for turn-on as well as to remain i n on-state. an ideal gate current waveform for ultra-fast switching of the sjt, while maintaining low gate drive losses, is shown in figure 23. figure 23: idealized gate current waveform gate currents, i g,pk /-i g,pk and voltages during turn-on and turn-off an sjt is rapidly switched from its blocking state to on-state, when the necessary gate charge, q g , for turn-on is supplied by a burst of high gate current, i g,on , until the gate-source capacitance, c gs , and gate-drain capacitance, c gd , are fully charged. , the i g,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the module and drive circuit. a voltage developed across the parasitic i nductance in the source path, l s , can de-bias the gate-source junc tion, when high drain currents begin to flow through the device. the applied gate voltage should be maintained high enough, above the v gs,on level to counter these effects. a high negative peak current, -i g,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. while sati sfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn-off transition. steady on-state after the device is turned on, i g may be advantageously lowered to i g,steady for reducing unnecessary gate drive losses. the i g,steady is determined by noting the dc current gain, h fe , of the device the desired i g,steady is determined by the peak device junction temperature t j during operation, drain current i d , dc current gain h fe , and a 50 % safety margin to ensure operating the device in the satu ration region with low on-state voltage drop by the equation: , , 1.5
? GA20SICP12-263 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 8 of 8 package dimensions: to-263 package outline note 1. controlled dimension is inch. di mension in bracket is millimeter. 2. dimensions do not include end fl ash, mold flash, material protrusions revision history date revision comments supersedes 2014/08/25 2 gate drive theory update 2014/06/23 1 updated characteristics 2013/12/11 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specificat ions and data in this document without noti ce. genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or i mplied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic cont rol and weapons systems, nor in applications where their failure may result in death , personal injury and/or property damage.
? GA20SICP12-263 june 2014 http://www.genesicsemi.com/comme rcial-sic/sic-modules-copack/ pg 1 of 1 ? spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website ( http://www.genesicsemi.com/images/products_s ic/igbt_copack/GA20SICP12-263_spice.pdf ) into ltspice (version 4) software for simulation of the GA20SICP12-263. * model of genesic semiconductor inc. * * $revision: 1.2 $ * $date: 23-jun-2014 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2014 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * * start of GA20SICP12-263 spice model * .subckt ga20sipc12 drain gate source q1 drain gate source ga20sipc12_q d1 source drain ga20sipc12_d1 d2 source drain ga20sipc12_d2 * .model ga20sipc12_q npn + is 5.00e-47 ise 1.26e-28 eg 3.23 + bf 65 br 0.55 ikf 700 + nf 1 ne 2 rb 2.60 + rc 0.045 trc1 8.50e-03 re 0.01 + xtb -1.2 cjc 6.98e-10 vjc 3 + mjc 0.5 cje 2.22e-09 vje 3 + mje 0.5 xti 3 mfg genesic_semi .model ga20sipc12_d1 d + is 4.55e-15 rs 0.055 n 1 + ikf 1000 eg 1.2 xti -2 + trs1 0.008 trs2 2.71739e-05 cjo 6.40e-10 + vj 0.469 m 1.508 fc 0.5 + tt 1.00e-10 .model ga20sipc12_d2 d + is 1.54e-22 rs 0.19 trs1 -0.004 + n 3.941 eg 3.23 ikf 19 + xti 0 fc 0.5 tt 0 .ends * end of GA20SICP12-263 spice model
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